The present invention relates to resource allocation, and more particularly to methods and apparatus for allocating image rendering resources, e.g., a CPU used to decode multiple images.
Video devices, such as television sets and personal computers, often process and then simultaneously display multiple images on a single display screen. For example, a computer may display multiple windows with a different image being displayed in each window. Television sets, e.g., with picture-in-picture capability, are another example of a device which processes and then simultaneously displays multiple images.
Image rendering, i.e., the processing of image data to prepare an image for display on a display device, often requires a substantial amount of resources. For example, image rendering may involve the use of a video decoder, bus, memory and/or CPU resources. A large number of processing operations involved in rendering most images. Accordingly, given a limited set of resources, it may not be possible to fully decode and display on a single screen, in real time, as many images as might be desired. The problem of limited image processing resources is particularly noticeable when attempting to simultaneously render and display large numbers of video images in real time.
The lack of unlimited processing resources to support multiple image decoding operations creates a need for methods and apparatus for determining how image rendering resources should be allocated. This is particularly the case when demands for available image processing resources exceed the available supply.
Accordingly, there is a need for methods and apparatus for determining which one of a plurality of image should be given image rendering priority when multiple images are being rendered for display on a single screen and there are insufficient resources to fully render all of the images. In the case of video decoding implemented using e.g., a CPU and/or a bus, this may involve determining which one of a plurality of images should be given decoding priority in terms of CPU and/or bus access.